Fundamentals of computer architecture: digital logic design, working up from the logic gate level to understand the function of a simple computer; machine-level programming to understand implementation of high-level languages; performance models of modern computer architectures to enable performance optimization of software; hardware primitives for parallelism and security.
CS 233 has several goals:
The first two goals we will address together as we teach you the principles of logic design through the implementation of a processor capable of executing a subset of the MIPS instruction set architecture (ISA). Along the way we will discuss how computers represent numbers, understand the decode/execute model, the design of finite state machines and more. Specifically we will test the following objectives:
As computers execute programs in machine language, we will address the third goal through an extensive discussion of machine language and its human readable counterpart, assembly language. We will demonstrate how features of modern programming languages (e.g., function calls, recursion, pointers, dynamic memory allocation, etc.) are implemented in assembly language. In addition, topics like compilation, linking, I/O programming, and interrupt programming will be covered. We will specifically test the following objectives:
The fourth goal will be addressed in three ways: 1) We will present an overview of the organization of modern computers (processor, memory, I/O system) demonstrating the key challenges and ideas (e.g., pipelining, caching, indirection, etc.) that influence their design, 2) we will present both theoretical and practical performance analysis techniques and analyze the performance of many parts of modern machines (processors, memory, caches, disks, networks), and 3) we will write code in high-level languages and assembly to optimize program execution. We will specifically test the following objectives:
While the previous goals focus primarily on single-processor systems, the last goal presents hardware mechanisms for implementing parallel processing. Specifically, we will discuss SIMD execution, cache coherence, memory consistency, and hardware synchronization primitives. As part of this discussion, we introduce concepts of race conditions, false sharing, and the need for memory barriers. We will specifically test the following objectives:
Officially, we have 50-minute lectures, three times a week and discussion/lab section once per week. Because of COVID-19, we will not be keeping strictly to the official registrar schedule. We will use two lectures time slots per week to support students during assigned group work. We will use one lecture time slot a week for open office hours, auxiliary group work time, or review sessions. We will not use our discussion/lab section time in any strict manner, though you are welcome to use that time to facilitate finding times to meet with your team members.
You will be assigned to a team of 3-4 students. Twice a week, your team will complete a collaborative, team-based exercise that will dig deeper into the core concepts in the pre-flights. If everyone on your team has completed and understood the pre-flights, we expect that these collaborative exercises will take about 1 hour and should take less than 2 hours. Everyone in your team will share the same score. You are encouraged to work together, checking and challenging each other’s understanding as these collaborative exercises will be graded such that you will need to answer each question correctly only once but you will lose points for each incorrect submission. At the end of each collaborative exercise, one team member (on a rotating basis) will be required to submit a write up, documenting code and design decisions. You will provide peer reviews of your teammates.
All textbooks are optional. Copies of the textbook (as well as others) are on reserve at Grainger Library.
Logic and Computer Design Fundamentals, by M. Morris Mano and Charles R. Kime. (Published by Prentice-Hall), 2008. Fourth Edition 2008 ISBN: 0-13-198926-X
Computer Organization & Design: The Hardware/Software Interface, by David A. Patterson and John L. Hennessy. (Published by Morgan Kaufmann) Second Edition: 1998 ISBN: 1-55860-428-6 Third Edition: 2004 ISBN: 1-55860-604-1 Fourth Edition 2008 ISBN-13: 978-0123744937
Verilog HDL: A Guide to Digital Design and Synthesis, by Samir Palnitkar. (Published by Prentice Hall). Second Edition:2003 ISBN: 0-13-044911-3
The first part of this course follows the first book Logic and Computer Design Fundamentals, but much of this material is available in an appendix of Computer Organization & Design: The Hardware/Software Interface.
Some of the discussion sections in the first part of the course consist of Verilog problems, for which the Verilog HDL book can be used as a reference. However, the Verilog material covered in this course is very basic, and you should be able to find on-line any references needed.
The second and third part of this course follows the book on Computer Organization & Design: The Hardware/Software Interface very closely, so it is highly recommended, but many students find they don’t refer to the book. Any of the second, third, or fourth editions are fine.
Throughout the semester, we will be using iverilog, gtkwave, gcc/g++, and SPIM, all of which are installed on the Linux EWS machines, but many of which you can set up on your own machine. We can, however, provide little assistance in getting this software running on your machine.
cs233.github.io has the schedule and lecture and section notes. Just about all course materials will be distributed on the web.
We’ll be using Piazza. Piazza is designed to reduce the time to getting your question answered and for easy navigation, but this in part relies on your appropriate usage. Please follow the following guidelines:
We will have web-based preflights before each class meeting that will be worth roughly 5% of your overall grade. These pre-flights will provide you with links to introductory videos and will be available in PrairieLearn. These preflights are intended to prepare you to contribute to your in-class group work. Most questions in the preflight will need to be answered correctly multiple times to receive full credit. Aside from the first few class meetings, preflights must be finished prior to class meetings to receive credit.
You will be assigned to a team of 3-4 students to work on longer, collaborative assessments in PrairieLearn during class meetings. All members of your group will receive the same grade on these assignments. These assessments will help you dive deeper into the course content and prepare you for the lab assignments. Most questions in these collaborative assessments will need to be answered only once and many will allow only one submission for full credit. Aside from the first few class meetings, group work muts be completed with 36 hours of class meetings, though it is expected that these assignments will be able to be completed during class time.
There will be 13 labs throughout the semester each weighted equally. See Lab Submission Policy below.
We’ll have a comprehensive final to cover the material that follows Quiz11 and a sampling of the material from the rest of the semester.
Submission: Code will be submitted through Github and occassionally PrairieLearn. Like any workplace would, we expect you to correctly check in your code. We will grade whatever was checked in most recently at the deadline. We won’t be lenient if you forget to check in your code or check in the wrong version. You can verify which version of your code is checked in using the web interface for Github.
Partners: For most labs, you can work individually or with 1 partner. The exceptions are labs declared as individual, and the SPIMbot tournament lab, where you must work in groups of two or three. You will specify your partners using the partners.txt file, by including the netids of all collaborators (your netid + any partners), one per line.
Late Submission: One lab’s second part (other than the SPIMbot tournament) can be submitted up to 48 hours late without penalty. Otherwise, a 10% penalty every 12 hours (or part thereof) will be assessed, up to a maximum of 48 hours. See our Submission Policy page for more details.
Style: Good style is important whenever writing code; We reserve the right to assign a 0 to any assignment that demonstrates total disregard for standard good style conventions.
Regrade requests for quizzes must be submitted within 48 hours of your quiz. Regrade requests must be submitted either as issues during your quiz or as a private piazza post after your quiz.
For labs, regrade requests must be submitted within 48 hours of the grade being released. The grade release announcements will have directions for asking grade-related questions and requested regrades.
All grades will be available via the Compass grade book. Please verify the accuracy of your grades often during the semester! Typos are unfortunately very possible in a class with many students.
Letter grades will be assigned based on your overall numeric score. Also, the top and bottom 1% in each range will receive plus and minus grades (i.e., 99% and above get an A+, [91%-99%) get an A, [90%,91%) get an A-, [89%,90%) get a B+). We reserve the right to lower these thresholds but we will never raise them.
Academic integrity is an important issue in general. The University expects you all to be familiar with Rule 33 in the Code of Policies and Regulations Applying to All Students. If we are able to pick out two nearly identical assignments out of 400, then cheating has likely occurred. All parties involved will receive a 0 on that assignment or quiz and their final course grade reduced by one letter grade (e.g., A->B, B->C, etc.). A second offense will result in a failing grade for the class.
Do NOT post your code into public code sharing tools such as Github. While you may not be cheating, you are enabling other students to cheat which is against the student code.
To obtain disability-related academic adjustments and/or auxiliary aids, students with disabilities must contact the course instructor and the Disability Resources and Educational Services (DRES) as soon as possible. To contact DRES, you may visit 1207 S. Oak St., Champaign, call 333-4603, e-mail firstname.lastname@example.org or go to the DRES website.
For instructions on how to handle accomodations with the computer-based testing facility, please see https://cbtf.engr.illinois.edu/#dres
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